SOPC中自定義元件的端口設置解析

ID:107189 · 發表于 2016-3-4 20:44

Nios II 嵌入式系統驅動設計（一）

最近一直在做SOPC自定義元件的設計及其驅動的編寫，今天先分享一些關于自定義元件端口設置的內容。

在版本8.0中，SOPC Builder已經集成了七十多個IP，用戶可以非常方便的應用這些元件，不過在實際應用的時候，有些元件并沒有包含在SOPC中，需要用戶自己編寫元件代碼，并集成進SOPC Builder里面，自定義元件的集成過程其實就是將元件通過Avalon總線兼容的端口掛載到Avalon總線上，因此最重要的一步就是設置元件的端口，使其能掛載到Avalon總線上。

在7.2版本之后，Quartus II在自定義元件端口設置方面做了很大的修改，下面是變更的內容。

Table 1. Current Avalon Interfaces Supported by the Component Editor
Interface Type	Default Name	Description	New Interface in v7.2
Master	avalon_master or m0	Defines an Avalon master port interface.	-
Slave	avalon_slave or s0	Defines an Avalon slave port interface.	-
Tri-State Slave	avalon_tristate_slave	Defines an Avalon tri-state port interface.	-
Clock Input	clock or clock_sink	Defines a clock and reset input interface for a component.	Y
Clock Output	clock_source	Defines a clock and reset output interface for components that generate clocks for SOPC Builder systems.	Y
Conduit Output or Input	conduit_start or conduit_end	Used for exporting signals to the top level of SOPC Builder systems. Conduit output and input interfaces are identical and imply no signal direction for the conduit interface. Conduits can contain input, output, and bidirectional signals.	Y
Interrupt Sender	interrupt_sender	Defines an interrupt output signal and the Avalon slave interface that is associated with generating the interrupt signal.	Y
Interrupt Receiver	interrupt_receiver	Defines an interrupt input signal and the Avalon master interface that is associated with receiving interrupt signals.	Y
Streaming Source	avalon_streaming_source	Defines an Avalon streaming source port interface.	Y
Streaming Sink	avalon_streaming_sink	Defines an Avalon streaming sink port interface.	Y

我們可以發現除了已有的Master，slave以及tri-state slave以外，還新增了流處理端口，中斷收發端口，時鐘及輸出端口。因為在7.2版本以后，除了Avalom-MM總線外，SOPC又新增了Avalon-ST總線，因此端口也相應的增加了。

下面列出在7.2版本后主端口和從端口所需的端口信號，表中還列出了和以前版本的端口比較。

*Table 1. Avalon-MM Slave with Global Clock, Reset, Interrupt Output, and Export Signals*
Signal Type	Direction	v7.1 and Earlier Interface	v7.2 and Later Interface
clk	Input	Global	Clock Input (1)
reset	Input	Global	Clock Input (1)
address	Input	Avalon Slave	Avalon Slave
read	Input	Avalon Slave	Avalon Slave
readdata	Output	Avalon Slave	Avalon Slave
write	Input	Avalon Slave	Avalon Slave
writedata	Input	Avalon Slave	Avalon Slave
waitrequest	Output	Avalon Slave	Avalon Slave
irq	Output	Avalon Slave	Interrupt Sender
my_export_signals	Input, Output, or Bidir	Global	Conduit

*Table 2. Avalon-MM Multi-Port Slave with Global Clock, Reset, and Export Signals*
Signal Type	Direction	v7.1 and Earlier Interface	v7.2 and Later Interface
clk	Input	Global	Clock Input (1)
reset	Input	Global	Clock Input (1)
s1_address	Input	Avalon S1 Slave	Avalon S1 Slave
s1_read	Input	Avalon S1 Slave	Avalon S1 Slave
s1_readdata	Output	Avalon S1 Slave	Avalon S1 Slave
s1_write	Input	Avalon S1 Slave	Avalon S1 Slave
s1_writedata	Input	Avalon S1 Slave	Avalon S1 Slave
s1_waitrequest	Output	Avalon S1 Slave	Avalon S1 Slave
s1_export_signals	Input, Output, or Bidir	Avalon S1 Slave	S1 Conduit
s2_address	Input	Avalon S2 Slave	Avalon S2 Slave
s2_read	Input	Avalon S2 Slave	Avalon S2 Slave
s2_readdata	Output	Avalon S2 Slave	Avalon S2 Slave
s2_write	Input	Avalon S2 Slave	Avalon S2 Slave
s2_writedata	Input	Avalon S2 Slave	Avalon S2 Slave
s2_waitrequest	Output	Avalon S2 Slave	Avalon S2 Slave
s2_export_signals	Input, Output, or Bidir	Avalon S2 Slave	S2 Conduit

*Table 3. Avalon-MM Master with Global Clock, Reset, Interrupt Input, and Export Signals*
Signal Type	Direction	v7.1 and Earlier Interface	v7.2 and Later Interface
clk	Input	Global	Clock Input (1)
reset	Input	Global	Clock Input (1)
address	Output	Avalon Master	Avalon Master
read	Output	Avalon Master	Avalon Master
readdata	Input	Avalon Master	Avalon Master
write	Output	Avalon Master	Avalon Master
writedata	Output	Avalon Master	Avalon Master
waitrequest	Input	Avalon Master	Avalon Master
irq	Input	Avalon Master	Interrupt Receiver
my_export_signals	Input, Output, or Bidir	Global	Conduit

*Table 4. Avalon-MM Multi-Port Slave with Interface-Specific Clocks and Export Signals*
Signal Type	Direction	v7.1 and Earlier Interface	v7.2 and Later Interface
s1_clk	Input	Avalon S1 Slave	S1 Clock Input (1)
s1_reset	Input	Avalon S1 Slave	S1 Clock Input (1)
s1_address	Input	Avalon S1 Slave	Avalon S1 Slave
s1_read	Input	Avalon S1 Slave	Avalon S1 Slave
s1_readdata	Output	Avalon S1 Slave	Avalon S1 Slave
s1_write	Input	Avalon S1 Slave	Avalon S1 Slave
s1_writedata	Input	Avalon S1 Slave	Avalon S1 Slave
s1_waitrequest	Output	Avalon S1 Slave	Avalon S1 Slave
s1_export_signals	Input, Output, or Bidir	Avalon S1 Slave	S1 Conduit
s2_clk	Input	Avalon S2 Slave	S2 Clock Input (1)
s2_reset	Input	Avalon S2 Slave	S2 Clock Input (1)
s2_address	Input	Avalon S2 Slave	Avalon S2 Slave
s2_read	Input	Avalon S2 Slave	Avalon S2 Slave
s2_readdata	Output	Avalon S2 Slave	Avalon S2 Slave
s2_write	Input	Avalon S2 Slave	Avalon S2 Slave
s2_writedata	Input	Avalon S2 Slave	Avalon S2 Slave
s2_waitrequest	Output	Avalon S2 Slave	Avalon S2 Slave
s2_export_signals	Input, Output, or Bidir	Avalon S2 Slave	S2 Conduit

*Table 5. Avalon-MM Multi-Port Master and Slave with Interface-Specific Clocks*
Signal Type	Direction	v7.1 and Earlier Interface	v7.2 and Later Interface
slave_clk	Input	Avalon Slave	Slave Clock Input (1)
save_reset	Input	Avalon Slave	Slave Clock Input (1)
slave_address	Input	Avalon Slave	Avalon Slave
slave_read	Input	Avalon Slave	Avalon Slave
slave_readdata	Output	Avalon Slave	Avalon Slave
slave_write	Input	Avalon Slave	Avalon Slave
slave_writedata	Input	Avalon Slave	Avalon Slave
slave_waitrequest	Output	Avalon Slave	Avalon Slave
master_clk	Input	Avalon Master	Master Clock Input (1)
master_reset	Input	Avalon Master	Master Clock Input (1)
master_address	Output	Avalon Master	Avalon Master
master_read	Output	Avalon Master	Avalon Master
master_readdata	Input	Avalon Master	Avalon Master
master_write	Output	Avalon Master	Avalon Master
master_writedata	Output	Avalon Master	Avalon Master
master_waitrequest	Input	Avalon Master	Avalon Master

確定了需要哪些端口后，需要編寫元件代碼（Verilog或VHDL），在端口命名中，Altera推薦用如下命名方式，以便在導入component editor之后能自動識別成相應的interface type。

__[_n]

interface type如下表所示：

比如下面的端口定義：

module my_slave_irq_component (
// Signals for Avalon-MM slave port “s1” with irq
csi_clockreset_clk; //clockreset clock interface
csi_clockreset_reset_n;//clockreset clock interface
avs_s1_address;//s1 slave interface
avs_s1_read; //s1 slave interface
avs_s1_write; //s1 slave interface
avs_s1_writedata; //s1 slave interface
avs_s1_readdata; //s1 slave interface
ins_irq0_irq; //irq0 interrupt sender interface
);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
input [7:0]avs_s1_address;
input avs_s1_read;
input avs_s1_write;
input [31:0]avs_s1_writedata;
output [31:0]avs_s1_readdata;
output ins_irq0_irq;
/* Insert your logic here */
endmodule

當元件設置好端口，并編寫完相應的Verilog或VHDL代碼之后，并可以通過SOPC Builder中的Component editor集成進SOPC Builder中，用戶并可以非常方便的調用。關于這部分內容請參考SOPC自定義元件的添加及運行。

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SOPC中自定義元件的端口設置解析