FPGA VGA顯示 verilog源碼仿真與資料分享

ID:240399 · 發表于 2018-9-27 19:24

FPGA 驅動vga顯示源碼仿真與資料都有

`timescale 1ns / 1ps
/*==============================================================================
Engineer : a fei
Module Hierarchy : top function module
Design Name : vga_module.v
Module Name : vga_module
Project Name : test_project_top.qsf
Target Devices : Altera
Tool versions : QUARTUSII11.0/Windows XP
Description : 顯示“囧”字，綠背景，藍框,800*600@60Hz
Dependencies :
Revision : 0.01 - File Created
Additional Comments : modify the pixer to 800X600@72Hz
==============================================================================*/
module vga_module(
input i_fpga_clk , //50MHz
input i_rst_n , //低電平復位
output o_vga_red ,
output o_vga_green ,
output o_vga_blue ,
output o_vga_hsync , //行同步信號
output o_vga_vsync //場同步信號
);
//================================================================================
// 4、Wire and reg declaration
//================================================================================
reg[9:0] r_x_cnt; //行坐標（這里包括了行同步、后沿、有效數據區、前沿）
reg[9:0] r_y_cnt; //列坐標（這里包括了場同步、后沿、有效數據區、前沿）
always @ (posedge i_fpga_clk or negedge i_rst_n)
if(!i_rst_n)
r_x_cnt <= 10'd0;
else if(r_x_cnt == 10'd1000)
r_x_cnt <= 10'd0; //行計數只記到1000
else
r_x_cnt <= r_x_cnt+1'b1;
always @ (posedge i_fpga_clk or negedge i_rst_n)
if(!i_rst_n)
r_y_cnt <= 10'd0;
else if(r_y_cnt == 10'd665)
r_y_cnt <= 10'd0; //場同步只記到665
else if(r_x_cnt == 10'd1000)
r_y_cnt <= r_y_cnt+1'b1;//每計數完一行，場同步就加一
else
r_y_cnt <= r_y_cnt;
//================================================================================
// 4、Wire and reg declaration
//================================================================================
wire w_vga_valid; //有效數據顯示區標志，當坐標不處于有效顯示區時，R、G、B三原色信號接的電平都必須拉底（0）*/
assign w_vga_valid = (r_x_cnt > 10'd180) && (r_x_cnt < 10'd980) //800*600
&& (r_y_cnt > 10'd35) && (r_y_cnt < 10'd635);
wire [9:0] w_x_pos;
wire [9:0] w_y_pos; //有效顯示區坐標
assign w_x_pos = r_x_cnt-10'd180;//
assign w_y_pos = r_y_cnt-10'd35;//
reg r_vga_hsync;
reg r_vga_vsync;
always @ (posedge i_fpga_clk or negedge i_rst_n)
if (!i_rst_n)
begin
r_vga_hsync <= 1'b0;
r_vga_vsync <= 1'b0;
end
else
begin
r_vga_hsync <= r_x_cnt <= 10'd50; //產生hsync信號（行同步）0-50
r_vga_vsync <= r_y_cnt <= 10'd6; //產生vsync信號（場同步）0-6
end
//================================================================================
// 4、Wire and reg declaration
//================================================================================
//顯示一個矩形框
wire a_dis,b_dis,c_dis,d_dis; //矩形框顯示區域定位
assign a_dis = ( (w_x_pos>=200) && (w_x_pos<=220) )
&& ( (w_y_pos>=140) && (w_y_pos<=460) );
assign b_dis = ( (w_x_pos>=580) && (w_x_pos<=600) )
&& ( (w_y_pos>=140) && (w_y_pos<=460) );
assign c_dis = ( (w_x_pos>=220) && (w_x_pos<=580) )
&& ( (w_y_pos>140) && (w_y_pos<=160) );
assign d_dis = ( (w_x_pos>=220) && (w_x_pos<=580) )
&& ( (w_y_pos>=440) && (w_y_pos<=460) );
wire e_dis,f_dis,g_dis,h_dis; //矩形框顯示區域定位
assign e_dis = ( (w_x_pos>=320) && (w_x_pos<=340) )
&& ( (w_y_pos>=320) && (w_y_pos<=410) );
assign f_dis = ( (w_x_pos>=460) && (w_x_pos<=480) )
&& ( (w_y_pos>=320) && (w_y_pos<=410) );
assign g_dis = ( (w_x_pos>=340) && (w_x_pos<=460) )
&& ( (w_y_pos>320) && (w_y_pos<=340) );
assign h_dis = ( (w_x_pos>=340) && (w_x_pos<=460) )
&& ( (w_y_pos>=390) && (w_y_pos<=410) );
wire i_dis,j_dis,k_dis,l_dis;
assign i_dis = ( (w_x_pos>=320) && (w_x_pos<=340) )
&& ( (w_y_pos>=210) && (w_y_pos<=290) );
assign j_dis = ( (w_x_pos>=460) && (w_x_pos<=480) )
&& ( (w_y_pos>=210) && (w_y_pos<=290) );
assign k_dis = ( (w_x_pos>=270) && (w_x_pos<=320) )
&& ( (w_y_pos>270) && (w_y_pos<=290) );
assign l_dis = ( (w_x_pos>=480) && (w_x_pos<=530) )
&& ( (w_y_pos>=270) && (w_y_pos<=290) );
//================================================================================
// 2、output
//================================================================================
assign o_vga_red = w_vga_valid ? (i_dis | j_dis | k_dis | l_dis): 1'b0;
assign o_vga_blue = w_vga_valid ? (a_dis | b_dis | c_dis | d_dis | e_dis | f_dis | g_dis | h_dis ) : 1'b0;
assign o_vga_green = w_vga_valid ? ~(a_dis | b_dis | c_dis | d_dis | e_dis | f_dis | g_dis | h_dis | i_dis | j_dis | k_dis | l_dis) : 1'b0;
assign o_vga_vsync = r_vga_vsync ;
assign o_vga_hsync = r_vga_hsync ;
//================================================================================
endmodule

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全部資料51hei下載地址：

M20_VGA display.zip (4.48 MB, 下載次數: 65)

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FPGA VGA顯示 verilog源碼仿真與資料分享

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